/* romInit.s - Motorola ads834x ROM initialization module */

/* Copyright 1984-2005 Wind River Systems, Inc. */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01a,19jan05,dtr   written from ads827x and ads85xx.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 8 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"

/*#include "romInit.h"*/

#include "processor.h"
#include "mpc83xx.h"
#include "MPC8313ERDB.h"
#define WRITEADR(reg1,reg2,addr32,val) \
	lis	reg1, HI(addr32); \
	ori	reg1, reg1, LO(addr32); \
	lis	reg2, HI(val); \
	ori	reg2, reg2, LO(val); \
	stw	reg2, 0(reg1)

#define WRITEOFFSET(regbase,reg2,offset,val) \
        lis	reg2, HI(val); \
        ori	reg2, reg2, LO(val); \
	stw	reg2, offset(regbase);
	
	/* internals */

	FUNC_EXPORT(_romInit)		/* start of system code */
	FUNC_EXPORT(romInit)		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	.text
	/* Hard Reset Configuration Word */
 .fill   8,1,HRCW_LOW_BYTE0 
 .fill   8,1,HRCW_LOW_BYTE1 
 .fill   8,1,HRCW_LOW_BYTE2 
 .fill   8,1,HRCW_LOW_BYTE3
 .fill   8,1,HRCW_HIGH_BYTE0 
 .fill   8,1,HRCW_HIGH_BYTE1 
 .fill   8,1,HRCW_HIGH_BYTE2 
 .fill   8,1,HRCW_HIGH_BYTE3

 .fill   192,1,0     /* The rest of the space are filled with zeros */




/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:
       bl cold		/* jump to the cold boot initialization */
	nop
	bl start
	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-2005 Wind River Systems, Inc."
	.align 2

cold:
       li      r3, BOOT_COLD   /* set cold boot as start type */
      
#if 0
	lis	r4, CONFIG_DEFAULT_IMMR@h
	ori	r4, r4, CONFIG_DEFAULT_IMMR@l

	lis	r3, CFG_IMMR@h
	ori	r3, r3, CFG_IMMR@l
	stw	r3, IMMRBAR(r4)
	isync
	
#endif


	lis	r4, CONFIG_DEFAULT_IMMR@h
	ori	r4, r4, CONFIG_DEFAULT_IMMR@l
	
	bl	1f
1:	mflr	r7

	lis	r3, CFG_IMMR@h
	ori	r3, r3, CFG_IMMR@l

	lwz	r6, IMMRBAR(r4)
	isync

	stw	r3, IMMRBAR(r4)
	lwz	r6, 0(r7)		/* Arbitrary external load */
	isync

	lwz	r6, IMMRBAR(r3)
	isync

start:
	bl	init_e300_core

	bl map_flash_by_law1

	lis r4, (CFG_MONITOR_BASE)@h
	ori r4, r4, (CFG_MONITOR_BASE)@l
	addi r5, r4, in_flash - _romInit + EXC_OFF_SYS_RESET
	mtlr r5
	blr

in_flash:	
	bl remap_flash_by_law0
	
	/* setup the bats */
	bl	setup_bats
	sync

	bl	init_e300_core
	/* setup the bats */
	bl	setup_bats
	sync	

	/*
	 * Cache must be enabled here for stack-in-cache trick.
	 * This means we need to enable the BATS.
	 * This means:
	 *   1) for the EVB, original gt regs need to be mapped
	 *   2) need to have an IBAT for the 0xf region,
	 *      we are running there!
	 * Cache should be turned on after BATs, since by default
	 * everything is write-through.
	 * The init-mem BAT can be reused after reloc. The old
	 * gt-regs BAT can be reused after board_init_f calls
	 * board_early_init_f (EVB only).
	 */
	/* enable address translation */
	bl	enable_addr_trans
	sync

	/* enable and invalidate the data cache */
	bl	dcache_enable
	sync

	bl	lock_ram_in_cache
	sync


#ifdef INCLUDE_PCI_UNUSED
        /* Set the pciAutoconfig check to FALSE */
	xor     r5,r5,r5                /* Zero r5 */
	lis     r6,HIADJ(PCI_AUTO_CONFIG_ADRS)                   
	addi	r6,r6,LO(PCI_AUTO_CONFIG_ADRS)
	stw     r5,0(r6)
#endif /* INCLUDE_PCI */



        /* initialize the stack pointer */

	lis	sp, HIADJ(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)
	addi	sp, sp, LO(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)
	
	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */
	
	
       /*init system ddr sdram in c */
	bl cpu_init_f
       
       bl init_ddr_sdram
       
	bl bspInitLocalBank1
	bl bspInitCPLDBank
	bl bspInitNandFlashBank
	
	lis 	sp, HIADJ (STACK_ADRS)
	addi	sp, sp, LO (STACK_ADRS)

	/* go to C entry point */
	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/*bl dcache_disable*/
	
	
       li  r3, BOOT_COLD   /* all set cold boot as start type , lijiaqiang */
	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

	
	 
        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)
 
        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)
 
        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	sub	r6, r6, r7		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */

	mtspr	LR, r6				/* save destination address*/
						/* into LR register */
	blr				/* jump to the C entry point */

init_e300_core: /* time t 10 */
	/* Initialize machine status; enable machine check interrupt */
	/*-----------------------------------------------------------*/

	li	r3, MSR_KERNEL			/* Set ME and RI flags */
	rlwimi	r3, r5, 0, 25, 25	/* preserve IP bit set by HRCW */

	SYNC						/* Some chip revs need this... */
	mtmsr	r3
	SYNC
	mtspr	SRR1, r3			/* Make SRR1 match MSR */


	lis	r3, CFG_IMMR@h

	/* Disable Wathcdog  */
	/*-------------------*/
	lwz r4, SWCRR(r3)
	/* Check to see if its enabled for disabling
	   once disabled by SW you can't re-enable */
	andi. r4, r4, 0x4
	beq 1f
	xor r4, r4, r4
	stw r4, SWCRR(r3)
1:

	/* Initialize the Hardware Implementation-dependent Registers */
	/* HID0 also contains cache control			*/
	/*------------------------------------------------------*/
	lis	r3, CFG_HID0_INIT@h
	ori	r3, r3, (CFG_HID0_INIT| HID0_ICFI | HID0_DCFI)@l
	SYNC
	mtspr	HID0, r3

	lis	r3, CFG_HID0_FINAL@h
	ori	r3, r3, (CFG_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
	SYNC
	mtspr	HID0, r3

	lis	r3, CFG_HID2@h
	ori	r3, r3, CFG_HID2@l
	SYNC
	mtspr	HID2, r3

	/* clear all BAT's					*/
	/*----------------------------------*/

	xor	r0, r0, r0
	mtspr	DBAT0U, r0
	mtspr	DBAT0L, r0
	mtspr	DBAT1U, r0
	mtspr	DBAT1L, r0
	mtspr	DBAT2U, r0
	mtspr	DBAT2L, r0
	mtspr	DBAT3U, r0
	mtspr	DBAT3L, r0
	mtspr	IBAT0U, r0
	mtspr	IBAT0L, r0
	mtspr	IBAT1U, r0
	mtspr	IBAT1L, r0
	mtspr	IBAT2U, r0
	mtspr	IBAT2L, r0
	mtspr	IBAT3U, r0
	mtspr	IBAT3L, r0
	SYNC

	/* invalidate all tlb's
	 *
	 * From the 603e User Manual: "The 603e provides the ability to
	 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
	 * instruction invalidates the TLB entry indexed by the EA, and
	 * operates on both the instruction and data TLBs simultaneously
	 * invalidating four TLB entries (both sets in each TLB). The
	 * index corresponds to bits 15-19 of the EA. To invalidate all
	 * entries within both TLBs, 32 tlbie instructions should be
	 * issued, incrementing this field by one each time."
	 *
	 * "Note that the tlbia instruction is not implemented on the
	 * 603e."
	 *
	 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
	 * incrementing by 0x1000 each time. The code below is sort of
	 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
	 *
	 */

	li	r3, 32
	mtctr	r3
	li	r3, 0
1:	tlbie	r3
	addi	r3, r3, 0x1000
	bdnz	 1b
	SYNC

	/* Done!						*/
	/*------------------------------*/
	blr

map_flash_by_law1:
	/* When booting from ROM (Flash or EPROM), clear the  */
	/* Address Mask in OR0 so ROM appears everywhere      */
	/*----------------------------------------------------*/
	lis	r3, (CFG_IMMR)@h  /* r3 <= CFG_IMMR    */
	lwz	r4, OR0@l(r3)
	li	r5, 0x7fff        /* r5 <= 0x00007FFFF */
	and	r4, r4, r5
	stw	r4, OR0@l(r3)     /* OR0 <= OR0 & 0x00007FFFF */

	/* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
	 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
	 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
	 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
	 * 0xFF800.  From the hard resetting to here, the processor fetched and
	 * executed the instructions one by one.  There is not absolutely
	 * jumping happened.  Laterly, the u-boot code has to do an absolutely
	 * jumping to tell the CPU instruction fetching component what the
	 * u-boot TEXT base address is.  Because the TEXT base resides in the
	 * boot ROM memory space, to garantee the code can run smoothly after
	 * that jumping, we must map in the entire boot ROM by Local Access
	 * Window.  Sometimes, we desire an non-0x00000 or non-0xFF800 starting
	 * address for boot ROM, such as 0xFE000000.  In this case, the default
	 * LBIU Local Access Widow 0 will not cover this memory space.  So, we
	 * need another window to map in it.
	 */
	lis r4, (FLASH_BASE_ADRS)@h
	ori r4, r4, (FLASH_BASE_ADRS)@l
	stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */

	/* Store 0x80000012 + log2(CFG_NOR_SIZE) into LBLAWAR1 */
	lis r4, (0x80000012)@h
	ori r4, r4, (0x80000012)@l
	li r5, CFG_NOR_SIZE
1:	srawi. r5, r5, 1	/* r5 = r5 >> 1 */
	addi r4, r4, 1
	bne 1b

	stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= Flash Size */
	blr

remap_flash_by_law0:
	/* Initialize the BR0 with the boot ROM starting address. */
	lwz r4, BR0(r3)
	li  r5, 0x7FFF
	and r4, r4, r5
	lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
	ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
	or  r5, r5, r4
	stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */

	lwz r4, OR0(r3)
	lis r5, ~((CFG_FLASH_SIZE << 4) - 1)
	or r4, r4, r5
	stw r4, OR0(r3)

	lis r4, (CFG_FLASH_BASE)@h
	ori r4, r4, (CFG_FLASH_BASE)@l
	stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */

	/* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */
	lis r4, (0x80000012)@h
	ori r4, r4, (0x80000012)@l
	li r5, CFG_FLASH_SIZE
1:	srawi. r5, r5, 1 /* r5 = r5 >> 1 */
	addi r4, r4, 1
	bne 1b
	stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */


	xor r4, r4, r4
	stw r4, LBLAWBAR1(r3)
	stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
	blr

setup_bats:
	addis	r0, r0, 0x0000

	/* IBAT 0 */
#if ((CFG_IBAT0L == 0) && (CFG_IBAT0U == 0))
	mtspr	IBAT0L, r0
	mtspr	IBAT0U, r0
#else
	addis	r4, r0, CFG_IBAT0L@h
	ori	r4, r4, CFG_IBAT0L@l
	addis	r3, r0, CFG_IBAT0U@h
	ori	r3, r3, CFG_IBAT0U@l
	mtspr	IBAT0L, r4
	mtspr	IBAT0U, r3
#endif
	isync

	/* DBAT 0 */
#if ((CFG_DBAT0L == 0) && (CFG_DBAT0U == 0))
	mtspr	DBAT0L, r0
	mtspr	DBAT0U, r0
#else
	addis	r4, r0, CFG_DBAT0L@h
	ori	r4, r4, CFG_DBAT0L@l
	addis	r3, r0, CFG_DBAT0U@h
	ori	r3, r3, CFG_DBAT0U@l
	mtspr	DBAT0L, r4
	mtspr	DBAT0U, r3
#endif
	isync

	/* IBAT 1 */
#if ((CFG_IBAT1L == 0) && (CFG_IBAT1U == 0))
	mtspr	IBAT1L, r0
	mtspr	IBAT1U, r0
#else
	addis	r4, r0, CFG_IBAT1L@h
	ori	r4, r4, CFG_IBAT1L@l
	addis	r3, r0, CFG_IBAT1U@h
	ori	r3, r3, CFG_IBAT1U@l
	mtspr	IBAT1L, r4
	mtspr	IBAT1U, r3
#endif
	isync

	/* DBAT 1 */
#if ((CFG_DBAT1L == 0) && (CFG_DBAT1U == 0))
	mtspr	DBAT1L, r0
	mtspr	DBAT1U, r0
#else
	addis	r4, r0, CFG_DBAT1L@h
	ori	r4, r4, CFG_DBAT1L@l
	addis	r3, r0, CFG_DBAT1U@h
	ori	r3, r3, CFG_DBAT1U@l
	mtspr	DBAT1L, r4
	mtspr	DBAT1U, r3
#endif
	isync

	/* IBAT 2 */
#if ((CFG_IBAT2L == 0) && (CFG_IBAT2U == 0))
	mtspr	IBAT2L, r0
	mtspr	IBAT2U, r0
#else
	addis	r4, r0, CFG_IBAT2L@h
	ori	r4, r4, CFG_IBAT2L@l
	addis	r3, r0, CFG_IBAT2U@h
	ori	r3, r3, CFG_IBAT2U@l
	mtspr	IBAT2L, r4
	mtspr	IBAT2U, r3
#endif
	isync

	/* DBAT 2 */
#if ((CFG_DBAT2L == 0) && (CFG_DBAT2U == 0))
	mtspr	DBAT2L, r0
	mtspr	DBAT2U, r0
#else
	addis	r4, r0, CFG_DBAT2L@h
	ori	r4, r4, CFG_DBAT2L@l
	addis	r3, r0, CFG_DBAT2U@h
	ori	r3, r3, CFG_DBAT2U@l
	mtspr	DBAT2L, r4
	mtspr	DBAT2U, r3
#endif
	isync

	/* IBAT 3 */
#if ((CFG_IBAT3L == 0) && (CFG_IBAT3U == 0))
	mtspr	IBAT3L, r0
	mtspr	IBAT3U, r0
#else
	addis	r4, r0, CFG_IBAT3L@h
	ori	r4, r4, CFG_IBAT3L@l
	addis	r3, r0, CFG_IBAT3U@h
	ori	r3, r3, CFG_IBAT3U@l
	mtspr	IBAT3L, r4
	mtspr	IBAT3U, r3
#endif
	isync

	/* DBAT 3 */
#if ((CFG_DBAT3L == 0) && (CFG_DBAT3U == 0))
	mtspr	DBAT3L, r0
	mtspr	DBAT3U, r0
#else
	addis	r4, r0, CFG_DBAT3L@h
	ori	r4, r4, CFG_DBAT3L@l
	addis	r3, r0, CFG_DBAT3U@h
	ori	r3, r3, CFG_DBAT3U@l
	mtspr	DBAT3L, r4
	mtspr	DBAT3U, r3
#endif
	isync

#if (CFG_HID2 & HID2_HBE)
	/* IBAT 4 */
#if ((CFG_IBAT4L == 0) && (CFG_IBAT4U == 0))
	mtspr	IBAT4L, r0
	mtspr	IBAT4U, r0
#else
	addis   r4, r0, CFG_IBAT4L@h
	ori     r4, r4, CFG_IBAT4L@l
	addis   r3, r0, CFG_IBAT4U@h
	ori     r3, r3, CFG_IBAT4U@l
	mtspr   IBAT4L, r4
	mtspr   IBAT4U, r3
#endif
	isync

	/* DBAT 4 */
#if ((CFG_DBAT4L == 0) && (CFG_DBAT4U == 0))
	mtspr	DBAT4L, r0
	mtspr	DBAT4U, r0
#else
	addis   r4, r0, CFG_DBAT4L@h
	ori     r4, r4, CFG_DBAT4L@l
	addis   r3, r0, CFG_DBAT4U@h
	ori     r3, r3, CFG_DBAT4U@l
	mtspr   DBAT4L, r4
	mtspr   DBAT4U, r3
#endif
	isync

	/* IBAT 5 */
#if ((CFG_IBAT5L == 0) && (CFG_IBAT5U == 0))
	mtspr	IBAT5L, r0
	mtspr	IBAT5U, r0
#else
	addis   r4, r0, CFG_IBAT5L@h
	ori     r4, r4, CFG_IBAT5L@l
	addis   r3, r0, CFG_IBAT5U@h
	ori     r3, r3, CFG_IBAT5U@l
	mtspr   IBAT5L, r4
	mtspr   IBAT5U, r3
#endif
	isync

	/* DBAT 5 */
#if ((CFG_DBAT5L == 0) && (CFG_DBAT5U == 0))
	mtspr	DBAT5L, r0
	mtspr	DBAT5U, r0
#else
	addis   r4, r0, CFG_DBAT5L@h
	ori     r4, r4, CFG_DBAT5L@l
	addis   r3, r0, CFG_DBAT5U@h
	ori     r3, r3, CFG_DBAT5U@l
	mtspr   DBAT5L, r4
	mtspr   DBAT5U, r3
#endif
	isync

	/* IBAT 6 */
#if ((CFG_IBAT6L == 0) && (CFG_IBAT6U == 0))
	mtspr	IBAT6L, r0
	mtspr	IBAT6U, r0
#else
	addis   r4, r0, CFG_IBAT6L@h
	ori     r4, r4, CFG_IBAT6L@l
	addis   r3, r0, CFG_IBAT6U@h
	ori     r3, r3, CFG_IBAT6U@l
	mtspr   IBAT6L, r4
	mtspr   IBAT6U, r3
#endif
	isync

	/* DBAT 6 */
#if ((CFG_DBAT6L == 0) && (CFG_DBAT6U == 0))
	mtspr	DBAT6L, r0
	mtspr	DBAT6U, r0
#else
	addis   r4, r0, CFG_DBAT6L@h
	ori     r4, r4, CFG_DBAT6L@l
	addis   r3, r0, CFG_DBAT6U@h
	ori     r3, r3, CFG_DBAT6U@l
	mtspr   DBAT6L, r4
	mtspr   DBAT6U, r3
#endif
	isync

	/* IBAT 7 */
#if ((CFG_IBAT7L == 0) && (CFG_IBAT7U == 0))
	mtspr	IBAT7L, r0
	mtspr	IBAT7U, r0
#else
	addis   r4, r0, CFG_IBAT7L@h
	ori     r4, r4, CFG_IBAT7L@l
	addis   r3, r0, CFG_IBAT7U@h
	ori     r3, r3, CFG_IBAT7U@l
	mtspr   IBAT7L, r4
	mtspr   IBAT7U, r3
#endif
	isync

	/* DBAT 7 */
#if ((CFG_DBAT7L == 0) && (CFG_DBAT7U == 0))
	mtspr	DBAT7L, r0
	mtspr	DBAT7U, r0
#else
	addis   r4, r0, CFG_DBAT7L@h
	ori     r4, r4, CFG_DBAT7L@l
	addis   r3, r0, CFG_DBAT7U@h
	ori     r3, r3, CFG_DBAT7U@l
	mtspr   DBAT7L, r4
	mtspr   DBAT7U, r3
#endif
	isync
#endif

	/* Invalidate TLBs.
	 * -> for (val = 0; val < 0x20000; val+=0x1000)
	 * ->   tlbie(val);
	 */
	lis	r3, 0
	lis	r5, 2

1:
	tlbie	r3
	addi	r3, r3, 0x1000
	cmp	0, 0, r3, r5
	blt	1b

	blr

enable_addr_trans:
	/* enable address translation */
	mfmsr	r5
	ori	r5, r5, (MSR_IR | MSR_DR)
	mtmsr	r5
	isync
	blr

icache_enable:
	mfspr	r3, HID0
	ori	r3, r3, HID0_ICE
	li	r4, HID0_ILOCK
	andc 	r3, r3, r4
	ori	r4, r3, HID0_ICFI
	isync
	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
	isync
	mtspr	HID0, r3	  /* clears invalidate */
	blr

dcache_enable:
	mfspr	r3, HID0
	li	r5, HID0_DCFI|HID0_DLOCK
	andc 	r3, r3, r5
	mtspr	HID0, r3		/* no invalidate, unlock */
	ori	r3, r3, HID0_DCE
	ori	r5, r3, HID0_DCFI
	mtspr	HID0, r5		/* enable + invalidate */
	mtspr	HID0, r3		/* enable */
	sync
	blr

dcache_disable:
	mfspr	r3, HID0
	lis	r4, 0
	ori	r4, r4, HID0_DCE|HID0_DLOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_DCI
	sync
	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
	sync
	mtspr	HID0, r3	/* clears invalidate */
	blr


lock_ram_in_cache:
	/* Allocate Initial RAM in data cache.
	 */
	lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h
	ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
	li	r2, ((CFG_INIT_RAM_END & ~31) + \
		     (CFG_INIT_RAM_ADDR & 31) + 31) / 32
	mtctr	r2
1:
	dcbz	  r0, r3
	addi	  r3, r3, 32
	bdnz  1b

	/* Lock the data cache */
	mfspr	r0, HID0
	ori	r0, r0, 0x1000
	sync
	mtspr	HID0, r0
	sync
	blr

unlock_ram_in_cache:
	/* invalidate the INIT_RAM section */
	 lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h	
	 ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l	
	 li	r2,512	
	 mtctr	r2
	1:	icbi	r0, r3	
	 dcbi	 r0, r3	
	 addi	r3, r3, 32
	 bdnz	1b	
	 sync			/* Wait for all icbi to complete on bus	*/	
	 isync	

	/* Unlock the data cache and invalidate it */	
	 mfspr   r3, HID0	
	 li	r5, HID0_DLOCK|HID0_DCFI	
	 andc	 r3, r3, r5		/* no invalidate, unlock */	
	 ori	r5, r3, HID0_DCFI	/* invalidate, unlock */	
	 mtspr	HID0, r5		/* invalidate, unlock */	
	 mtspr	HID0, r3		/* no invalidate, unlock */	
	 sync
	 blr


	
light:
    lis	r24, (MPC8xxx_SICRH_ADDR+CCSBAR)@h
    addi r24,r24,(MPC8xxx_SICRH_ADDR+CCSBAR)@l

    lis  r22,(0xFC33C100)@h
    addi r22,r22,(0xFC33C100)@l
    stw r22,GPIO_DIR(r24)


    lis	r24, (MPC8xxx_GPIO_PHY_BASE+CCSBAR)@h
    addi r24,r24,(MPC8xxx_GPIO_PHY_BASE+CCSBAR)@l

    lis  r22,(0x0000FE00)@h
    addi r22,r22,(0x0000FE00)@l
    stw r22,GPIO_DIR(r24)

    lis  r22,(0x00000000)@h
    addi r22,r22,(0x00000000)@l
    stw r22,GPIO_ODR(r24)

    lis  r22,(0x00000000)@h
    addi r22,r22,(0x00000000)@l
    stw r22,GPIO_DAT(r24)
    blr


light_off_all:
    lis	r24, (MPC8xxx_GPIO_PHY_BASE+CCSBAR)@h
    addi r24,r24,(MPC8xxx_GPIO_PHY_BASE+CCSBAR)@l

    lis  r22,(0x0000FE00)@h
    addi r22,r22,(0x0000FE00)@l
    stw r22,GPIO_DIR(r24)

    lis  r22,(0x00000000)@h
    addi r22,r22,(0x00000000)@l
    stw r22,GPIO_ODR(r24)

    lis  r22,(0x00001000)@h
    addi r22,r22,(0x00001000)@l
    stw r22,GPIO_DAT(r24)
    blr		





